The semiconductor integrated circuit (IC) industry has experienced rapid growth. Technological advances in IC materials and design have produced generations of ICs where each generation has smaller and more complex circuits than the previous generation. As the semiconductor industry has progressed into nanometer technology process nodes in pursuit of higher device density, higher performance, and lower costs, challenges from both fabrication and design issues have resulted in the development of three-dimensional designs, such as the fin field effect transistor (FinFET). FinFETs are fabricated with a thin vertical “fin” (or fin structure) extending from a substrate. The channel of the FinFET is formed in this vertical fin. A gate is provided over three sides (e.g., wrapping) the fin. Advantages of the FinFET may include reducing the short channel effect and raising the current flow.
Although existing FinFETs and methods of fabricating FinFETs have been generally adequate for their intended purposes, they have not been entirely satisfactory in all respects. For example, as the size of FinFET device structure has been reduced, problems (e.g., poor step coverage, opening overhang, void formation, and increased contact resistance) may occur when contact metal materials are filled into contact openings (e.g., vias or trenches) with small critical dimension (CD). Therefore, it is a challenge to form reliable contact structures at smaller and smaller sizes.